1. Field of the Invention
The present invention relates generally to the field of semiconductor integrated circuits and, more particularly, to an improved SiGe device with SiGe-embedded dummy pattern that encircles the SiGe device, which is capable of alleviating the micro-loading effect during the epitaxial growth of SiGe.
2. Description of the Prior Art
As known in the art, stress can be introduced in the channel region of a MOS transistor to increase carrier mobility, thereby enhancing the performance of the MOS transistor. Generally, it is desirable to induce tensile stress in the channel region of an NMOS device in a source-to-drain direction, and to induce compressive stress in the channel region of a PMOS device in a source-to-drain direction. Typically, to induce compressive stress in the channel region of a PMOS transistor, epitaxially grown SiGe (also referred to as SiGe stressor) is formed in the source and drain regions of the PMOS devices. Since SiGe has a greater lattice constant than silicon, it expands after annealing and induces compressive stress to the channel region in a source-to-drain direction.
However, the conventional SiGe technology suffers from the influence of micro-loading effect, which occurs due to a difference in pattern densities on a single die. The micro-loading effect leads to variation of epitaxial growth rates between a region of a higher density and a region of a lower density. Due to the difference in growth rates, the thickness of the resulting SiGe film becomes non-uniform. In addition, the composition of the epitaxial SiGe stressor in an isolated active region usually differs from that in a densely packed active region. Such non-uniformities may alter the stress level of the epitaxial SiGe stressor and adversely affect device performance.
Accordingly, there is a strong need in this industry to provide an improved SiGe device and method for alleviating the micro-loading effect, while at the same time overcoming the deficiencies of the prior art.